1. Technical Field
The present invention relates to data processing and, in particular, to multiple instruction issue in a high performance processor. Still more particularly, the present invention provides a method and apparatus for control signal memoization in a multiple instruction issue microprocessor.
2. Description of Related Art
As higher frequency microarchitectures are demanded by the marketplace, computer architects have strived to deliver these processors. While in the past increases in frequency have directly translated into performance, recent architectures have suffered from cycles per instruction (CPI) degradation often negating the benefits of higher frequency operation. A recent example includes the Pentium® 4 processor, which produced inferior performance for several benchmarks when executed at the same or slightly higher frequency than a previous Pentium® III processor. Pentium® 4 and Pentium® III are trademarks of Intel Corporation.
More complicated microprocessors include multiple execution units. For example, a microprocessor may include two integer execution units, two floating-point execution units, a comparison execution unit, and a load/store execution unit. In this example, the microprocessor may execute up to six instructions at a time. A pipeline in the processor may include an instruction fetch phase, an instruction decode phase, an instruction issue phase, an instruction execution phase, a memory read/write phase, and a retire phase. The microprocessor may then potentially fetch, decode, issue, and execute instructions in groups of up to six. In the above example, the microprocessor may fetch up to two integer instructions, two floating-point instructions, a compare instruction, and a load or store instruction as a group. To issue an instruction group, the microprocessor must compute a control vector for the group.
The root cause for CPI degradation in aggressive multiple issue microprocessors is often tracked down to the deep pipelines necessary to continue ensuring increases in operating frequencies. A common occurrence in these pipelines is the generation and regeneration of various control flow signals. Often, the control signals generated in many of these pipeline stages are repetitive. Therefore, a great deal of processing overhead is spent on computing control signals in multiple instruction issue microprocessors.